1. Field of the Invention
The invention relates to shift register latch circuit means contained in LSI circuitry conforming to LSSD rules and techniques. The shift register latch circuit means is utilized for checking and testing the LSI circuitry.
2. Cross-Reference to Related Applications
1. U.S. patent application Ser. No. 066,130 entitled "Improved Level Sensitive Scan Design System", filed Aug. 13, 1979 by S. DasGupta et al., of common assignee granted as U.S. Pat. No. 4,293,919 on Oct. 6, 1981.
2. U.S. patent application Ser. No. 062,932 entitled "Method and Arrangement of Testing Sequential Circuits Represented by Monolithically Integrated Semiconductor Circuits", filed July 26, 1979 by J. Hajdu and G. Knauft, of common assignee granted as U.S. Pat. No. 4,298,980 on Nov. 3, 1981.
3. U.S. patent application Ser. No. 934,936 entitled "Module Interconnection Testing Scheme", filed Aug. 18, 1978 by S. J. Hong, of common assignee, granted as U.S. Pat. No. 4,241,307 on Dec. 23, 1980.
4. U.S. patent application Ser. No. 974,641 entitled "Chip and Wafer Configuration and Testing Method for Large-Scale-Integrated Circuits" filed Dec. 29, 1978 by F. F. Tsui, of common assignee, granted as U.S. Pat. No. 4,244,048 on Jan. 6, 1981.
5. U.S. patent application Ser. No. 929,480 entitled "Test Circuitry For Module Interconnection Network" filed July 31, 1978, by M. T. McMahon, Jr., of common assignee, granted as U.S. Pat. No. 4,220,917 on Sept. 2, 1980.
6. U.S. patent application Ser. No. 104,481 filed Dec. 17, 1979 entitled "Automatic Testing of Complex Semiconductor Components With Test Equipment Having Less Channels Than Those Required By The Component Under Test" by H. D. Schnurmann, of common assignee, granted as U.S. Pat. No. 4,348,759 on Sept. 7, 1982.
7. U.S. patent application Ser. No. 264,995 filed May 18, 1981 entitled "Shift Register Latch Circuit Means Contained in LSI Circuitry Conforming to Level Sensitive Scan Design (LSSD) Rules and Techniques and Utilized At Least in Part for Check and Test Purposes" by Arnold Blum and of common assignee.
As a result of increasing integration, and in particular large-scale integration (LSI) and very large scale integration (VLSI), the direct access to a circuit group in a physical unit (e.g., a chip, a module, etc.) has become increasingly difficult and restricted. This is attributable both to the considerable increase in the number of circuits used in the LSI and VLSI unit and to the microscopical dimensions such circuits have. Thus, the testing of such circuits has become one of the main problems during the manufacture of highly integrated circuits.
The testing of an LSI and VLSI unit is further aggravated by the presence of inaccessible storage elements and latch circuits which are generally embedded along with the logical combinational networks. As it is impossible to test and check the logical states of these embedded latches, it is equally impossible to test the appertaining logical networks. In spite of this, it is not possible to do without a reliable and thorough test of the various LSI and VLSI components and units during manufacturing and operation.
A number of U.S. Patents, briefly discussed below, concern a system design method and discipline (or rules and techniques) for meeting the above requirements. These rules and techniques all come under the title "LSSD" (Level-Sensitive Scanning Design). A feature all of the known solutions have in common is that a built-in circuit is required for each LSI unit, by means of which the logical state of the unit is explicitly tested in full and/or is tested at a limited number of I/O pins, using certain I/O methods. These requirements can be met by arranging for each latch of the logical system in the unit to be associated with shift register latches and by subsequently combining or organizing these shift register latches (SRLs) in the form of one or several shift register data channels, the I/O stages of which are accessible from the outside.
Detailed operation by means of this SRL arrangement (wherein each shift register latch comprises a master latch and a slave latch) for different test requirements are expressly set out and specified in U.S. Pat. No. 3,761,695, FIGS. 7 through 9 of U.S. Pat. No. 3,784,907 and a number of other U.S. patents and publications fully identified hereinafter.
The most important requirements may be summarized as follows: In the test mode, particular logical test patterns required, are serially entered and subsequently shifted to the appropriate latch positions if the unit is operated in the shift mode, i.e., by inhibiting the system clock and by triggering the shift clock pulse to the unit. As a result, the latch states of the individual circuits supply the pulses required for testing the appertaining logical networks. Then the test patterns are passed on through the networks by implementing one or several steps of the function mode, i.e., by normal system clock energization. The response patterns of the logical networks to the pulses applied are latched by the system latches in a known manner as a function of particular states in the design of the system, which often replace the test patterns originally entered. For testing, the system returns to the shift mode, issuing the response patterns. By means of the conventional shift registers, which are generally used in practice for SRLs, it is possible to check and test at the expense of the hardware, which in certain cases may be rather uneconomical. This is largely due to the fact that to each system latch a second latch has to be added, permitting the former to function as an SRL circuit. Namely, each SRL is comprised of a master latch and a slave latch.
In view of this, conventional shift registers use two latches (a master and a slave) for each shift register latch (SRL) stage. Shifting in and shifting out operations are effected by the parallel application of a two-phase clock sequence. (For example, an A-clock and a B-clock are provided).
The shift register featured in U.S. Pat. No. 3,783,254 uses two DC latch circuits (a master latch circuit and a slave latch circuit) for each shift register latch stage. Shifting in and shifting out is effected by a two-phase clock system (A-clock and B-clock) which is applied in parallel to a first and a second latch circuit (master and slave) of each stage of the shift register.
To reduce the expenditure incurred by the double latch circuits, GE-OS No. 2 723 594 proposes a shift register for check and test purposes which, while having the same function as known registers, necessitates only half as many latch circuits. [GE OS No. 2723594 corresponds to U.S. Pat. No. 4,051,353 entitled "Accordion Shift Register and Its Application In the Implementation of Level Sensitive Logic System" granted Sept. 27, 1977 to Hua-Tung Lee and of common assignee herewith]. For this purpose, a latch circuit is associated with each circuit or each circuit group for a particular logical function or storage function. The latch circuits forming states of the shift register, to the input of which check and test information is applied. At the output of the shift register particular bit patterns are emitted as a function of the check and test information entered as well as of the state of the integrated circuit to be tested. As a function of a shift clock control, A- and B-pulses alternately increment the latch circuits in a shift register forming a test channel. This activates the different latch circuits at a clock time (A or B) either once or several times. As a result, the information in the shift register is compressed and the decompressed, i.e., pulled apart in the manner of an accordion.
The solution, set forth in U.S. Pat. No. 4,051,353, uses a relatively high proportion of slave circuits, namely fifty percent in relation to the master circuits. In addition, its line structure and control are extensive.